?002 fairchild semiconductor corporation IRFP150 rev. b IRFP150 40a, 100v, 0.055 ohm, n-channel power mosfet this n-channel enhancement mode silicon gate power ?ld effect transistor is an advanced power mosfet designed, tested, and guaranteed to withstand a speci?d level of energy in the breakdown avalanche mode of operation. all of these power mosfets are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. these types can be operated directly from integrated circuits. formerly developmental type ta17431. features 40a, 100v ? ds(on) = 0.055 ? single pulse avalanche energy rated soa is power dissipation limited nanosecond switching speeds linear transfer characteristics high input impedance related literature - tb334 ?uidelines for soldering surface mount components to pc boards symbol packaging jedec style to-247 top view ordering information part number package brand IRFP150 to-247 IRFP150 note: when ordering, include the entire part number. g d s source drain drain (flange) gate data sheet january 2002 no t recommended for new designs possible substitute pr oduct IRFP150n
?002 fairchild semiconductor corporation IRFP150 rev. b absolute maximum ratings t c = 25 o c, unless otherwise speci?d IRFP150 units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v ds 100 v drain to gate voltage (r gs = 20k ?) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 100 v continuous drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d 40 a t c = 100 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d 26 a pulsed drain current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 160 a gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v gs 20 v maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .p d 180 w linear derating factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.44 w/ o c single pulse avalanche energy rating (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as 150 mj operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 125 o c. electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss v gs = 0v, i d = 250 a (figure 10) 100 - - v gate to threshold voltage v gs(th) v gs = v ds , i d = 250 a 2.0 - 4.0 v zero-gate voltage drain current i dss v ds = rated bv dss , v gs = 0v - - 25 a v ds = 0.8 x rated bv dss , v gs = 0v, t j = 125 o c - - 250 a on-state drain current (note 2) i d(on) v ds > i d(on) x r ds(on)max , v gs = 10v 40 - - a gate to source leakage i gss v gs = 20v - - 100 na drain to source on resistance (note 2) r ds(on) v gs = 10v, i d = 22a (figures 8, 9) - 0.045 0.055 ? forward transconductance (note 2) g fs v ds 20v, i d = 20a (figure 12) 13 20 - s turn-on delay time t d(on) v dd = 50v, i d = 40a, r gs = 6.8 ? , r l = 1.2 ? mosfet switching times are essentially independent of operating temperature -1524ns rise time t r - 140 210 ns turn-off delay time t d(off) -6089ns fall time t f - 90 140 ns total gate charge (gate to source + gate to drain) q g(tot) v gs = 10v, i d = 40a, v ds = 0.8 x rated bv dss . i g(ref) = 1.5ma (figure 14) gate charge is essentially independent of operating temperature - 70 110 nc gate to source charge q gs -20- nc gate to drain ?iller?charge q gd -30- nc input capacitance c iss v gs = 0v, v ds = 25v, f = 1.0mhz (figure 11) - 2000 - pf output capacitance c oss - 1000 - pf reverse-transfer capacitance c rss - 350 - pf internal drain inductance l d measured from the drain lead, 6mm (0.25in) from the package to the center of the die modified mosfet symbol showing the internal devices inductances - 5.0 - nh internal source inductance l s measured from the source lead, 6mm (0.25in) from the header to the source bonding pad - 12.5 - nh junction to case r jc - - 0.70 o c/w junction to ambient r ja free air operation - - 30 o c/w l s l d g d s IRFP150
?002 fairchild semiconductor corporation IRFP150 rev. b source to drain diode speci?ations parameter symbol test conditions min typ max units continuous source to drain current i sd modified mosfet symbol showing the integral reverse p-n junction diode - - 40 a pulse source to drain current (note 3) i sdm - - 170 a source to drain diode voltage (note 2) v sd t j = 25 o c, i sd = 40a, v gs = 0v (figure 13) - - 2.5 v reverse recovery time t rr t j = 25 o c, i sd = 40a, di sd /dt = 100a/ s 98 - 530 ns reverse recovered charge q rr t j = 25 o c, i sd = 40a, di sd /dt = 100a/ s 0.41 - 2.5 c notes: 2. pulse test: pulse width 300 s, duty cycle 2%. 3. repetitive rating: pulse width limited by max junction temperature. see transient thermal impedance curve (figure 3). 4. v dd = 10v, starting t j = 25 o c, l = 170 h, r g = 50 ? , peak i as = 40a. typical performance curves unless otherwise speci?d figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance g d s 0 50 100 150 0 t c , case temperature ( o c) power dissipation multiplier 0.2 0.4 0.6 0.8 1.0 1.2 t c , case temperature ( o c) 50 75 100 25 150 50 40 30 0 20 i d, drain current (a) 10 125 z jc , transient thermal impedance 1 0.1 10 -2 10 -2 10 -5 10 -4 10 -3 0.1 1 10 t 1 , rectangular pulse duration (s) 10 -3 single pulse duty factor: d = t 1 /t 2 notes: peak t j = p dm x z jc x r jc + t c t 2 p dm t 1 t 2 0.5 0.2 0.1 0.05 0.01 0.02 IRFP150
?002 fairchild semiconductor corporation IRFP150 rev. b figure 4. forward bias safe operating area figure 5. output characteristics figure 6. saturation characteristics figure 7. transfer characteristics figure 8. drain to source on resistance vs gate voltage and drain current figure 9. normalized drain to source on resistance vs junction temperature typical performance curves unless otherwise speci?d (continued) 10 2 10 110 10 2 1 i d , drain current (a) v ds , drain to source voltage (v) 10 s 100 s 1ms 10ms 10 3 operation in this region is limited by r ds(on) 10 3 t j = max rated single pulse t c = 25 o c dc v ds , drain to source voltage (v) 10 20 30 40 050 60 48 36 0 24 i d , drain current (a) v gs = 5.0v v gs = 6.0v v gs = 4.0v pulse duration = 80 s 12 v gs = 7.0v v gs = 10v v gs = 8v duty cycle = 0.5% max v ds , drain to source voltage (v) 1234 05 60 48 36 0 24 i d , drain current (a) 12 v gs = 8v v gs = 5v v gs = 6v v gs = 4v v gs = 7v v gs = 10v pulse duration = 80 s duty cycle = 0.5% max i ds(on) , drain to source current (a) v sd , gate to source voltage (v) 100 10 1 0.1 0 246810 t j = 150 o c t j = 25 o c pulse duration = 80 s duty cycle = 0.5% max v ds = 20v 120 i d , drain current (a) 30 60 90 0 150 0.40 0.32 0.24 0 0.16 r ds(on) , drain to source v gs = 20v 0.08 v gs = 10v on resistance pulse duration = 80 s duty cycle = 0.5% max 2.5 1.5 0.5 80 -60 t j , junction temperature ( o c) normalized drain to source 2.0 1.0 0 0 60 120 160 on resistance -20 -40 20 40 100 140 pulse duration = 80 s duty cycle = 0.5% max i d = 22a, v gs = 10v IRFP150
?002 fairchild semiconductor corporation IRFP150 rev. b figure 10. normalized drain to source breakdown voltage vs junction temperature figure 11. capacitance vs drain to source voltage figure 12. transconductance vs drain current figure 13. source to drain diode voltage figure 14. gate to source voltage vs gate charge typical performance curves unless otherwise speci?d (continued) 1.25 1.05 0.85 60 -60 t j , junction temperature ( o c) normalized drain to source 1.15 0.95 0.75 -20 20 100 160 breakdown voltage 0 -40 40 80 120 140 i d = 250 a 12 102 5 10 2 c, capacitance ( p f) v ds , drain to source voltage (v) 5000 4000 3000 2000 1000 0 5 c rss c iss c oss v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gd i d , drain current (a) 12 24 36 48 060 30 24 18 0 12 g fs , transconductance (s) 6 t j = 150 o c t j = 25 o c pulse duration = 80 s duty cycle = 0.5% max v ds = 20v i sd , source to drain current (a) v sd , source to drain voltage (v) 10 3 10 2 10 1 0 0.6 1.2 1.8 2.4 3.0 t j = 25 o c t j = 150 o c pulse duration = 80 s duty cycle = 0.5% max q g , gate charge (nc) 30 60 90 120 0 150 4 20 8 v gs , gate to source voltage (v) 16 v ds = 80v i d = 40a 12 0 v ds = 50v v ds = 20v IRFP150
?002 fairchild semiconductor corporation IRFP150 rev. b test circuits and waveforms figure 15. unclamped energy test circuit figure 16. unclamped energy waveforms figure 17. switching time test circuit figure 18. resistive switching waveforms figure 19. gate charge test circuit figure 20. gate charge waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 v gs r l r g dut + - v dd t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 0.3 f 12v battery 50k ? v ds s dut d g i g(ref) 0 (isolated v ds 0.2 f current regulator i d current sampling i g current sampling supply) resistor resistor same type as dut q g(tot) q gd q gs v ds 0 v gs v dd i g(ref) 0 IRFP150
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
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